Review Problems for CS 30200 / ECE 46810 Exam 2 Spring 2019 Version 1.1. (I fixed a typo in Problem 3.) The exam is over Chapters 7, 8, 13, 15, 16.1, 18.1-18.3, 21, and 22 from the textbook. http://pages.cs.wisc.edu/~remzi/OSTEP/ http://pages.cs.wisc.edu/~remzi/OSTEP/cpu-sched.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/cpu-sched-mlfq.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-intro.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-mechanism.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-paging.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-beyondphys.pdf http://pages.cs.wisc.edu/~remzi/OSTEP/vm-beyondphys-policy.pdf 1.) What is an advantage of a large time quantum? What is a disadvantage? Why would a MLFQ scheduler have longer time quantums for lower priority queues? 2.) What is the difference between a preemptive scheduler and a non­preemptive scheduler? 3.) Suppose that an operating system has a round robin priority scheduler with a time quantum of 50 (and no scheduling overhead). Consider the following set of processes. (Assume that lower numbers denote lower priority and higher numbers denote higher priority). Process Arrival-Time Run-Time Priority 0 0 150 2 1 50 30 3 2 100 130 4 3 120 80 1 4 170 90 4 a) Create a time line illustrating the execution of these processes assuming that scheduling decisions are only made whenever a process terminates or a time quantum expires (so the scheduler is non-preemptive). b) Create a time line illustrating the execution of these processes assuming that scheduling decisions are only made whenever a process terminates, a time quantum expires, or a process becomes ready, that is, it arrives in the queue (so the scheduler is preemptive). 4.) For the following parts, use the following set of processes (all the processes have the same arrival time). Process Run-Time Priority 0 150 2 1 30 3 2 130 5 3 80 1 4 90 4 a) Using FCFS (based on process number), what is the average wait time for the example process set? b) Using FCFS (based on process number), what is the average turnaround time? c) Using SJF, what is the average wait time? d) Using SJF, what is the average turnaround time? e) Using priority scheduling, what is the average wait time? f) Using priority scheduling, what is the average turnaround time? g) Using RR scheduling with a time quantum of 40 and no scheduling overhead, what is the average wait time? h) Using RR scheduling with a time quantum of 40 and no scheduling overhead, what is the average turnaround time? i) Using RR scheduling with a time quantum of 40 and 10 units of time for scheduling overhead (dispatching, context switching, etc.) what is the average wait time? j) Using RR scheduling with a time quantum of 40 and 10 units of time for scheduling overhead (dispatching, context switching, etc.) what is the average turnaround time? k) For each of FCFS, SJF, priority scheduling, and RR (with a time quantum of 40) scheduling policies, create a time line illustrating the execution of the processes in the example process set. 5. Explain two differences between virtual addresses and physical addresses. 6. In a base-and-bound virtual memory system, explain how if a process modifies an arbitrary location in its virtual memory space, that change is not reflected at the same address of other processes. 7. In a paged virtual memory system, explain how if a process modifies an arbitrary location in its virtual memory space, that change is not reflected at the same address of other processes. 8. How does a base-and-bound virtual memory system prevent a process from accessing physical memory that is not allocated to the process? 9. How does a paged virtual memory system prevent a process from accessing physical memory that is not allocated to the process? 10. In a paged virtual memory system, why does the page size have to be a power of two? 11. In a paged virtual memory system, can the computer's physical memory address space be larger than a process's virtual memory address space? Explain your answer. (Note: A computer's "physical memory address space" is the number of bits for the frame number (PFN) plus the number of bits for the offset. A process's "virtual memory address space" is the number of bits for a page number (VPN) plus the number of bits for the offset.) 12. In a paged virtual memory system, can a process's virtual memory address space be larger than the computer's physical memory address space? Explain your answer. 13. In a paged virtual memory system, can a process's allocated virtual memory be larger than the computer's physical? That is, can a process have more pages allocated to it than there are page frames in physical memory? Explain your answer. 14. In a base-and-bound virtual memory system, explain how two processes can share physical memory. 15. In a paged virtual memory system, explain how two processes can share physical memory. 16. A page table entry (PTE) contains a page frame number (PFN) and additional meta-data about the page frame. Give three examples of meta-data bits that might be in a PTE. 17. What is a "page fault"? List the steps to process a page fault. 18. Consider a virtual address space of 64 pages of 1,024 bytes each, mapped onto a physical memory of 32 page frames. a.) How many bits are there is a virtual address? b.) How many bits are there in a physical address? c.) How are the bits divided between page number, frame number, and offset? 19. Consider a virtual address space of 32 pages with a 4KB page size, mapped onto a physical memory of 16 page frames. a.) How many bits are there is a virtual address? b.) How many bits are there in a physical address? c.) How are the bits divided between page number, frame number, and offset? 20. Give two benefits that a demand paged virtual memory system has over a non-demand paged virtual memory system. 21. In a demand paged virtual memory system, what is the purpose of the allocation policy? What is the purpose of the replacement policy? 22. A demand paged virtual memory system must have a "fetch policy" that decides when a page should be loaded into primary memory. The simplest fetch policy is to load a page only when it has been page faulted. What is another possible fetch policy and what advantage might it have over the simplest one? (Hint: prefetch) 23. A certain computer system implements a paged virtual memory system. Each process has a 16MB virtual memory space. The page size is 1024 bytes. The physical memory size for the system is 2MB. How many bits are in a virtual memory address? _______ How many bits are in a physical memory address? _______ What is the number of pages in a virtual address space? _______ What is the number of page frames in the system? _______ What is the maximum number of valid entries in a page table? _______ Draw an address translation diagram that would help someone visualize how addresses are translated in this system. Your diagram should show the sizes of virtual and physical addresses and how they are broken down into fields. It should show how a page table is used and what the dimensions of a page table are. 24. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space and a 24-bit physical address space. Assume that the first 6 bits of a virtual address index the page table and the rest of the bits are the page offset. A process has the following indexed page table. Index | Page Table Entry (PTE) 0 | 0x3800 1 | 0x3600 2 | 0x3200 3 | 0x1000 Each page table entry gives a hexadecimal page frame addresses. Translate the following two hexadecimal VM addresses into their corresponding hexadecimal physical address. Hint: Translate the VM address to binary first. Translate the binary VM address to a binary PM address. Translate the binary PM address into hexadecimal. VM Address 0x084B is _____________________ in Physical Memory VM Address 0x0C78 is _____________________ in Physical Memory 25. This problem is about what can be done when a process is larger than physical memory, that is, a process has more virtual pages than there are physical page frames. Assume that a process has four pages (numbered 0,1,2,3) in its virtual address space but the computer has only three physical page frames (numbered 0,1,2). The following tables show two possible sequences of referenced virtual page numbers by the running process. Write down in the empty slots below each page reference the virtual page that is loaded into each of the physical page frames just after the page reference (in other words, what does the process's page table look like just after each page reference?). Also, write down the total number of page hits and misses. Use the "Leased Recently Used" (LRU) page replacement policy in both cases, so you replace the contents of the page frame that was used the farthest back in time. Page Referenced: 0 1 2 3 0 1 2 3 Page Frame 0: Page Frame 1: Page Frame 2: # of hits = # of misses = Page Referenced: 0 1 0 1 2 3 2 3 Page Frame 0: Page Frame 1: Page Frame 2: # of hits = # of misses = 26. Suppose a computer has 4 physical pages frames, and a process references its virtual pages (page numbers 0 through 7) in the following order: 0 2 1 3 5 4 6 3 7 4 7 3 3 5 5 3 1 1 1 7 2 3 4 1 a) Suppose the kernel uses FIFO page replacement algorithm. How many page faults would the process have? Which page references are page faults? b) Suppose the kernel uses LRU as the page replacement algorithm. How many page faults would the process have? Which page references are page faults? c) Suppose the kernel uses the optimal page replacement algorithm. How many page faults would the process have? Which page references are page faults? 27. Consider the two-dimensional array int A[16][128]; where A[0][0] is at virtual address 512 in a paged memory system with pages of size 256 words and each int is one word. Suppose that this array is stored in "row major" form, which means that each row of 128 ints is stored in contiguous memory locations. (Notice that a column will not be stored contiguously.) The code for a small process that manipulates the matrix resides in page 1 (virtual addresses 256 to 511). Thus, every instruction fetch will be from page 1. Suppose that this process is allocated just three page frames (one for code and two for data). How many page faults are generated by the following array-initialization loops, using LRU replacement and assuming that page frame 1 already contains the process code and the other two page frames are initially empty? a.) for (int i = 0; i < 16; i++) for (int j = 0; j < 128; j++) A[i][j] = 0 b.) for (int j = 0; j < 128; j++) for (int i = 0; i < 16; i++) A[i][j] = 0;